The invention relates generally to phase locked loops, and more particularly to a lock detector for two or more phase locked loops.
A phase locked loop (PLL) adjusts the output frequency and/or phase of a clock signal synthesized by a voltage-controlled oscillator (VCO) to match a reference clock signal. The VCO clock signal loops back as a feedback signal through a loop divider that translates the frequency of the VCO signal to become a VCO divided signal. A phase detector then compares the phases of the VCO divided signal and its reference clock signal. The VCO adjusts the VCO clock signal according to this phase comparison. Such PLLs are well known and have a wide variety of applications in areas such as communication devices and other types of digital electronics.
Usually, a PLL is considered to be in lock when the phase difference between the VCO divided signal and the reference clock signal is within a certain tolerance. A PLL will often have a lock detector to indicate whether the PLL is locked. Lock detectors enable a decision to use the VCO clock signal if the PLL is in lock. Alternatively, if the lock detector indicates the PLL is not in lock, one can chose to not use the VCO clock signal. Certain applications require two phase locked loops such as in a master/slave arrangement wherein the master PLL""s VCO clock signal is frequency divided and serves as the reference clock to a slave PLL. In such dual PLL applications, it would be advantageous to determine whether both PLLs are in lock. This, however, would require two conventional PLL lock detectors. Replacing these two lock detectors with a single PLL lock detector would lead to a more compact design, consume less power, and provide more on-chip integration for the same power budget.
Accordingly, there is a need in the art for a single PLL lock detector that can determine whether both PLLs in a dual PLL system are each in lock.
In accordance with one aspect of the invention, a lock detector receives a first and a second signal. A first phase detector produces the first signal that indicates whether a frequency divided version of a VCO clock signal from a first phase locked loop is out of phase with the first phase locked loop""s reference clock signal by a predetermined number of VCO clock cycles. A second phase detector produces the second signal which that indicates whether a frequency divided version of a VCO clock signal from a second phase locked loop is out of phase with the second phase locked loop""s VCO clock signal second by a predetermined number of the second phase locked loop""s VCO clock cycles. Based upon the first and second signals, the lock detector determines whether the first and second phase locked loops are each locked.
In accordance with another aspect of the invention, a method of detecting lock in a system having a first and a second phase locked loop is provided. The method includes a first act of determining whether the first phase locked loop is in lock using a lock detector. A second act determines whether the second phase locked loop is locked using the lock detector. Should the first and second phase locked loops each be locked, the system is declared locked.
A more complete understanding of embodiments of the present invention will be afforded to those skilled in the art, as well as a realization of additional advantages thereof, by a consideration of the following detailed description of one or more embodiments. Reference will be made to the appended sheets of drawings that will first be described briefly.